IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
The relative priority of one DMA channel with respect to the other (Bit [5])
Acceptance of DMA requests from Timer 2 (Bit [4])
Byte or Word transfers (Bit [0])
Processor Internal Clock
Power-Save
Divisor
x1, x2
PLL
(/2 to /128)
Mux
clkouta
clkoutb
Drive enable
Time Delay
6 ±2.5nS
Mux
Drive enable
Figure 10. DMA Unit
4.21 DMA Priority
With the exception of word accesses to odd memory locations or between locked memory
addresses, DMA transfers have a higher priority than CPU transfers. Because the CPU cannot
access memory during a DMA transfer and a DMA transfer cannot be suspended by an interrupt
request, continuous DMA activity will increase interrupt delay. An NMI request halts any DMA
activity, however, enabling the CPU to respond promptly to the request.
4.22 Asynchronous Serial Port
The asynchronous serial port employs standard industry communication protocols in its
implementation of full duplex, bi-directional data transfers. The port can be either the source or
destination of DMA transfers.
The following features are supported:
Full-duplex data transfers
7-, 8-, or 9-bit data transfers
Odd, even, or no parity
One or two stop bits
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