IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
There are three sources of DMA requests for both DMA channels:
The channel request pin (drq1–drq0)
Timer 2
The system software.
Each channel may be programmed to have a different priority either to resolve a simultaneous
DMA request or to interrupt a transfer on the other channel.
4.19 DMA Operation
The PCB contains six registers for each DMA channel to control and specify the operation of the
channel (see Figure 10):
Two registers to store a 20-bit source address
Two registers to store a 20-bit destination address
One 16-bit transfer-count register
One 16-bit control register
The number of DMA transfers required is designated in the DMA Transfer Count register and
may contain up to 64 Kbytes or words. It will end automatically. DMA channel function is
defined by the control registers. Like the other five registers, these may be changed at any time
(including during a DMA transfer) and are implemented immediately.
4.20 DMA Channel Control Registers
See Section 5.1.8, D1CON (0dah) and D0CON (0cah). The DMA channel control registers
specify the following:
Whether the data destination is in memory or I/O space (Bit [15])
Whether the destination address is incremented, decremented, or unchanged after each
transfer (Bits [14–13])
Whether the data source is in memory or I/O space (Bit [12])
Whether the source address is incremented, decremented, or unchanged after each
transfer (Bits [11–10])
Whether DMA transfers cease upon reaching a designated count (Bit [9])
Whether the last transfer generates an interrupt (Bit [8])
Synchronization mode (Bits [7–6])
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