IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
4.17 Timer Control
The IA186EM and IA188EM each have three 16-bit programmable timers. Timer 0 and Timer 1
each has an input and output connected to external pins that permits it to count or to time events
as well as to produce variable duty-cycle waveforms or non-repetitive waveforms. Timer 1 can
also be configured as a Watchdog timer.
Because Timer 2 does not have external connections, it is confined to internal functions such as
real-time coding, time-delay applications, a prescaler for Timer 0 and Timer 1, or to synchronize
DMA transfers.
The Peripheral Control Block contains eleven 16-bit registers to control the programmable
timers. Each timer-count register holds the present value of its associated timer and may be read
from or written to whether or not the timer is in operation. The microcontroller increments the
value of the timer-count register when a timer event takes place.
The value stored in a timer’s associated maximum count register determines its maximum count
value. Upon reaching it, the timer count register is reset to 0 in the same clock cycle that this
count was attained. The timer count register does not store this maximum value. Both Timer 0
and Timer 1 have a primary and a secondary maximum count register that permits each to
alternate between two discrete maximum values.
Timer 0 and Timer 1 may have the maximum count registers configured in either primary only or
both primary and secondary. If the primary only is configured to operate, on reaching the
maximum count, the output pin will go low for one clock period. If both the primary and
secondary registers are enabled, the output pin reflects the state of the register in control at the
time. This generates the required waveform that is dependent on the two values in the maximum
count registers.
Because they are polled every fourth clock period, the timers can operate at a quarter of the
internal clock frequency. Although an external clock may be used, the timer output may take six
clock cycles to respond to the input.
4.18 Direct Memory Access (DMA)
DMA frees the CPU from involvement in transferring data between memory and peripherals
over either one or both high-speed DMA channels. Data may be transferred from memory to
I/O, I/O to memory, memory to memory, or I/O to I/O. DMA channels can be connected to the
asynchronous serial port.
The IA186EM supports the transfer of both bytes and words to and from even or odd addresses.
It does not support word transfers to memory that is configured for byte accesses. The IA188EM
does not support word transfers at all. Each data transfer will take two bus cycles (a minimum of
8 clock cycles).
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