IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
4.7
Chip Selects
Chip-select generation is programmable for memories and peripherals. Programming is also
available to produce ready- and wait-state generation plus latched address bits a1 and a2. For all
memory and I/O cycles, the chip-select lines are active within their programmed areas,
regardless of whether they are generated by the internal DMA unit or the CPU.
There are six chip-select outputs for memories and a further six for peripherals whether in
memory or I/O space. The memory chip-selects are able to address three memory ranges,
whereas the peripheral chip-selects are used to address 256-byte blocks that are offset from a
programmable base address. Writing to a chip-select register enables the related logic even if the
pin in question has another function (e.g., if the pin is programmed to be a PIO).
4.8
Chip-Select Timing
For normal timing, the ucs_n and lcs_n outputs are asserted with the non-multiplexed address
bus.
4.9
Ready- and Wait-State Programming
Each of the memory or peripheral chip-select lines can have a ready signal programmed that can
be the ardy or srdy signal. The chip-select control registers (UMCS, LMCS, MMCS, PACS, and
MPCS) have a single bit that selects whether the external ready signal is to be used or not (R2,
Bit [2]). R1 and R0 (Bits [1–0]) in these registers control the number of wait states that are
inserted during each access to a memory or peripheral location (from 0 to 3). The control
registers for pcs3_n–pcs0_n use three bits, R3, R1–R0 (Bits [3], [1–0]) to provide 5, 7, 9, and 15
wait-states in addition to the original values of 0 to 3 wait states.
In the case where an external ready has been selected as required, internally programmed wait-
states will always be completed before the external ready can finish or extend a bus cycle. As an
example, consider a system in which the number of wait states to be inserted has been set to 3.
The external ready pin is sampled by the processor during the first wait cycle. The access is
completed after 7 cycles (4 cycles plus 3 wait cycles) if the ready is asserted. Alternatively, if
the ready is not asserted during the first wait cycle, the access is prolonged until ready is asserted
and two more wait states are inserted followed by t4.
4.10 Chip Select Overlap
Overlapping chip selects are configurations where more than one chip select is asserted for the
same physical address. For example, if PCS is configured in I/O space with LCS or any other
chip select configured for memory, address 00000h is not overlapping the chip selects.
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