IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Processor Internal Clock
Mux
Power-Save
Divisor
(/2 to /128)
x1, x2
PLL
clkouta
clkoutb
Drive enable
Time Delay
6 ±2.5nS
Mux
Drive enable
Figure 9. Organization of Clock
4.4
Power-Save Mode
The operation of the CPU and peripherals operate at a slower clock frequency when in power
save mode, reducing power consumption and thermal dissipation. Should an interrupt occur, the
microcontroller returns to its normal operating frequency automatically on the internal clock’s
next rising edge in t3. Any clock-dependent devices should be reprogrammed for the change in
frequency during the power-save mode period.
4.5
Initialization and Reset
The highest priority interrupt, res_n (Reset) must be held low for 1 mS during power-up to
initialize the microcontroller correctly. This operation makes the device cease all instruction
execution and local bus activity. The microcontroller begins instruction execution at physical
address FFFF0h when res_n becomes inactive and after an internal processing interval with
ucs_n is asserted and three wait states. Reset also sets up certain registers to predetermined
values and resets the Watchdog timer.
4.6
Reset Configuration Register
The data on the address/data bus (ad15–ad0 for the IA186EM, ao15–ao8 and ad7–ad0 for the
IA188EM) are written into the Reset Configuration register when reset is low. This data is
system dependent and is held in the Reset Configuration register after Reset is de-asserted. This
configuration data may be placed on the address/data bus by using weak external pull-up and
pull-down resistors or applied to the bus by an external driver, as the processor does not drive the
bus during reset. It is a method of supplying the software with some initial data after a reset; for
example, option jumper positions.
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