XMC4500
XMC4000 Family
Electrical Parameters
Table 30
Power Supply Parameters (cont’d)
Symbol Values
Min. Typ. Max.
Parameter
Unit
Note /
Test Condition
Wake-up time from Deep
Sleep to Active mode
−
−
−
ms
Defined by the
wake-up of the
Flash module,
see
Section 3.2.9
Wake-up time from
Hibernate mode
−
−
−
ms
Wake-up via
power-on reset
event, see
Section 3.3.2
1) CPU executing code from Flash, all peripherals idle.
2) CPU executing code from Flash.
3) CPU in sleep, all peripherals idle, Flash in Active mode.
4) CPU in sleep, Flash in Active mode.
5) CPU in sleep, peripherals disabled, after wake-up code execution from RAM.
6) To wake-up the Flash from its Sleep mode, fCPU ≥ 1 MHz is required.
7) OSC_ULP operating with external crystal on RTC_XTAL
8) OSC_ULP off, Hibernate domain operating with OSC_SI clock
9) Test Power Loop: fSYS = 120 MHz, CPU executing benchmark code from Flash, all CCUs in 100kHz timer
mode, all ADC groups in continuous conversion mode, USICs as SPI in internal loop-back mode, CAN in
500kHz internal loop-back mode, interrupt triggered DMA block transfers to parity protected RAMs and FCE,
DTS measurements and FPU calculations.
The power consumption of each customer application will most probably be lower than this value, but must be
evaluated separately.
10) IDDP decreases typically by approximately 6 mA when fSYS decreases by 10 MHz, at constant TJ
11) Sum of currents of all active converters (ADC and DAC)
Data Sheet
58
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
