XC835/836
Electrical Parameters
3.3.5
SSC Timing
3.3.5.1 SSC Master Mode Timing
Table 22 provides the SSC master mode timing in the XC835/836.
Table 22
SSC Master Mode Timing1) (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limit Values
Unit
Min.
2 * TSSC
0
Max.
–
3
2)
SCLK clock period
MTSR delay from SCLK
t0
t1
CC
ns
ns
CC
SR
SR
MRST set-up to SCLK
MRST hold from SCLK
t2
t3
32
0
–
–
ns
ns
1) Not subject to production test, verified by design/characterisation.
2) TSSCmin = TCPU = 1/fCPU. When fCPU = 24 MHz, t0 = 83.3 ns. TCPU is the CPU clock period.
t0
SCLK1)
t1
t1
1)
MTSR
t2
t3
Data
MRST1)
valid
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_Tmg1
Figure 15
SSC Master Mode Timing
Data Sheet
43
V1.2, 2011-03
INFINEON [ Infineon ]
