XC835/836
Electrical Parameters
3.3.5.2 SSC Slave Mode Timing
Table 23 provides the SSC slave mode timing in the XC835/836.
Table 23
SSC Slave Mode Timing1) (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limit Values
Unit
Min.
4 * TSSC
0
Max.
–
29
2)
SCLK clock period
MRST delay from SCLK
t0
t1
SR
ns
ns
CC
SR
SR
MTSR set-up to SCLK
MTSR hold from SCLK
t2
t3
32
0
–
–
ns
ns
1) Not subject to production test, verified by design/characterisation.
2) TSSCmin = TCPU = 1/fCPU. When fCPU = 24 MHz, t0 = 166.7 ns. TCPU is the CPU clock period.
t0
SCLK1)
t2
t3
Data Valid
MTSR1)
MRST1)
t1
1)
This timing is based on the following setup : CON.PH = CON.PO = 0.
Figure 16
SSC Slave Mode Timing
Data Sheet
44
V1.2, 2011-03
INFINEON [ Infineon ]
