XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
The XC228x also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector
Trap
Trap
Location1) Number Priority
Reset Functions
–
RESET
xx’0000H
00H
III
Class A Hardware Traps:
•
•
•
•
System Request 0
Stack Overflow
Stack Underflow
Software Break
SR0
STKOF
STKUF
SR0TRAP
STOTRAP
STUTRAP
xx’0008H
xx’0010H
xx’0018H
02H
04H
06H
08H
II
II
II
II
SOFTBRK SBRKTRAP xx’0020H
Class B Hardware Traps:
•
•
•
•
System Request 1
Undefined Opcode
Memory Access Error
Protected Instruction
Fault
SR1
BTRAP
xx’0028H
xx’0028H
xx’0028H
xx’0028H
0AH
0AH
0AH
0AH
I
I
I
I
UNDOPC BTRAP
ACER
PRTFLT
BTRAP
BTRAP
•
Illegal Word Operand
Access
ILLOPA
BTRAP
xx’0028H
0AH
I
Reserved
–
–
–
–
[2CH - 3CH] [0BH -
0FH]
–
Software Traps:
Any
Any
Current
CPU
Priority
•
TRAP Instruction
[xx’0000H - [00H -
xx’01FCH] 7FH]
in steps of
4H
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet
46
V0.91, 2007-02
Draft Version
INFINEON [ Infineon ]
