XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
tpD
tpE
tpRDY
tpF
CLKOUT
RD, WR
tc10
tc20
tc31
tc30
D15-D0
(read)
Data In
tc25
D15-D0
(write)
Data Out
tc31
tc30
tc31
tc30
READY
Synchronous
Not Rdy
READY
tc31
tc31
tc30
tc30
READY
Asynchron.
Not Rdy
READY
MCT05559
Figure 22
READY Timing
Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”)
a READY-controlled waitstate is inserted (tpRDY),
sampling the READY input active at the indicated sampling point (“Ready”)
terminates the currently running bus cycle.
Note the different sampling points for synchronous and asynchronous READY.
This example uses one mandatory waitstate (see tpE) before the READY input is
evaluated.
Data Sheet
100
V0.91, 2007-02
Draft Version
INFINEON [ Infineon ]
