TLE9879QXA40
Capture/Compare Unit 6 (CCU6)
18
Capture/Compare Unit 6 (CCU6)
18.1
Feature Set Overview
This section gives an overview over the different building blocks and their main features.
Timer 12 Block Features
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Three capture/compare channels, each channel can be used either as capture or as compare channel
Generation of a three-phase PWM supported (six outputs, individual signals for high-side and low-side
switches)
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16-bit resolution, maximum count frequency = peripheral clock
Dead-time control for each channel to avoid short-circuits in the power stage
Concurrent update of T12 registers
Center-aligned and edge-aligned PWM can be generated
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Multiple interrupt request sources
Hysteresis-like control mode
Timer 13 Block Features
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One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock
Concurrent update of T13 registers
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Additional Specific Functions
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Block commutation for brushless DC-drives implemented
Position detection via hall-sensor pattern
Noise filter supported for position input signals
Automatic rotational speed measurement and commutation control for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
18.2
Introduction
The CCU6 unit is made up of a Timer T12 block with three capture/compare channels and a Timer T13 block with
one compare channel. The T12 channels can independently generate PWM signals or accept capture triggers, or
they can jointly generate control signal patterns to drive DC-motors or inverters.
A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible generation
of interrupt request signals provide efficient software-control.
Data Sheet
58
Rev. 1.0, 2015-04-30
INFINEON [ Infineon ]
