OPTIREG™ SBC TLE9274QXV33
High-speed CAN transceiver
1) Not subject to production test, specified by design.
2) Not subject to production test, specified by design, S2P - Method; f = 10 Mhz.
3) Voltage value valid for time < tTXDCAN_TO
4) Rtests between (VS/VCAN) and 0 V (GND).
.
5) VSYM shall be observed during dominant and recessive state and also during the transition dominant to recessive and
vice versa while TxD is simulated by a square signal (50% duty cycle), a frequency of 1 MHz.
6) tRec=tbit(RXD) -tbit(BUS)
.
7) Not subject to production test, tolerance defined by internal oscillator tolerance.
V
TXDCAN
VIO
GND
t
t
VDIFF
td(L),T
td(H),T
Vdiff, rd_N
Vdiff, dr_N
t d(L),R
td(H),R
t
t
loop,r
VRXDCAN
VIO
loop,f
0.8 x VIO
0.2 x VIO
GND
t
Figure 22 Timing diagrams for dynamic characteristics
Datasheet
59
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
