TLE9263QX
System Features
A wake event due to cyclic sense in SBC Mode will set the respective bit WK1_WU, WK2_WU, or WK3_WU.
During Cyclic Sense, WK_LVL_STAT is updated only with the sampled voltage levels of the WKx pins in SBC
Normal or SBC Stop Mode.
The functionality of the sampling and different scenarios are depicted in Figure 7 to Figure 9. The behavior in SBC
Stop and SBC Sleep Mode is identical except that in Stop Mode INT will be triggered to signal a change of WK
input levels and in SBC Sleep Mode, VCC1 will power-up instead.
HS on
Cyclic Sense
Periode
HS switch
Filter time
tFWK1
Filter time
tFWK1
On Time
t
1st sample taken
as reference
Wake detection possible
on 2nd sample
Figure 7
Wake Input Timing
HS
Filter time
High
Low
Switch
open
closed
WK
High
Low
n-1
Learning
Cycle
WKn-1= High
n
n+1
n+2
WKn+1 = Low
WKn = WKn+1
ꢁ
WKn+2= High
WKn+2 ≠WKn+ 1
ꢁwake event
WKn= Low
WKn ≠WKn-1
ꢁwake event
no wake
INT
High
Low
INT &
WK Bit Set
Figure 8
Cyclic Sense Example in SBC Stop Mode, HSx starts “OFF”/LOW, GND based WKx input
Data Sheet
34
Rev. 1.1, 2014-09-26
INFINEON [ Infineon ]
