TLE9263QX
System Features
HS
Filter time
High
Low
Spike
Switch
open
closed
WK
High
Low
n-1
n
n+1
n+2
WK = WKn+1 = Low
n
(but ignored because
change during filter time )
WKn = WKn+1
WKn+2= High
WKn+2 ≠WKn+ 1
ꢁwake event
Learning
Cycle
WKn-1= Low
WKn= Low
WKn = WKn-1
ꢁno wake event
VCC1
ꢁ
no wakTe reavennst ition to:
High
SBC Sleep Mode
SBC Normal Mode
INT &
WK Bit Set
Low
Start of
Cyclic Sense
Figure 9
Cyclic Sense Example in SBC Sleep Mode, HSx starts “OFF”/HIGH,
GND based WKx input
The cyclic sense function will not work properly anymore in case of following conditions:
•
in case SBC Fail-Safe Mode is entered: The respective HS Switch will be disabled and the respective wake
pin will be changed to static sensing
•
In SBC Normal, Stop, or Sleep Mode in case of an overcurrent, overtemperature, under- or overvoltage (in
case function is selected) event: the respective HS switch will be disabled
Note:The internal timers for cyclic sense are not disabled automatically in case the HS switch is turned off due to
above mentioned failures.This must be considered to avoid loss of wake events.
5.2.1.2
Cyclic Sense in Low Power Mode
If cyclic sense is intended for SBC Stop or SBC Sleep Mode mode, it is necessary to activate the cyclic sense in
SBC Normal Mode before going to the low power mode. A wake event due to cyclic sense will set the respective
bit WK1_WU, WK2_WU or WK3_WU. In Stop Mode the wake event will trigger an interrupt, in Sleep Mode the
wake event will send the device via Restart Mode to Normal Mode. Before returning to SBC Sleep Mode, the wake
status register WK_STAT_1 and WK_STAT_2 needs to be cleared. Trying to go to SBC Sleep mode with
uncleared wake flags, such as WKx_WU the SBC will directly wake-up from Sleep Mode by going via Restart
Mode to Normal Mode, a reset is issued. The WKx_WU bit is seen as source for the wake. This is implemented
in order not to loose an wake event during the transition.
Data Sheet
35
Rev. 1.1, 2014-09-26
INFINEON [ Infineon ]
