TLE 6244X
3.9.5 Timing
1. Cycle-Time
B
C
C
t cyc
t lead
t lag
200
100
150
ns
ns
ns
(referred to master)
2. Enable Lead Time
(referred to master)
3. Enable Lag Time
(referred to master)
4. Data Valid CL = 50pF (5 MHz)
Data Valid CL = 200pF (2MHz)
(referred to TLE6244X)
C
C
t v
t v
100
150
ns
ns
5. Data Setup Time
(referred to master)
C
C
C
C
C
C
C
t su
50
20
ns
ns
6. Data Hold Time
(referred to master)
t h
7. Disable Time
t dis
100
ns
(referred to TLE6244X)
8. Transfer Delay
t dt
150
50
ns
(referred to master)
9. Select time
t sel
t acc
tSCKH
tSCKL
tdld
nsec
µsec
ns
(referred to master)
10. Access time
8.35
50
(referred to master)
11. Serial clock high time
(referred to master)
12. Serial clock low time
13. Disable Lead Time
14. Disable Lag Time
C
C
120
250
250
ns
ns
C
tdlg
ns
Final Data Sheet
60
V4.2, 2003-08-29
INFINEON [ Infineon ]
