TLE 6244X
3.9.1 Input SCK
3.9.1.1 Low Level
3.9.1.2 High Level
3.9.1.3 Hysteresis
3.9.1.4 Input Capacity
SPI clock input
B
B
C
C
A
USCKL
USCKH
1.0
V
V
2.0
∆U
SCK
0.1
0.6
10
50
V
CSCK
-ISCK
pF
µA
3.9.1.5 Input Current Pull up current source connected
to VDD
10
20
20
20
3.9.2 Input SS
Slave select signal
3.9.2.1 Low Level
3.9.2.2 High Level
3.9.2.3 Hysteresis
TLE6244X is selected
B
B
C
C
USSL
USSH
∆USS
CSS
1.0
V
V
2.0
0.1
0.6
10
V
3.9.2.4 Input Capaci-
ty
pF
3.9.2.5 Input Current Pull up current source connected
to VDD
A
-ISS
10
50
µA
3.9.3 Input SI
SPI data input
3.9.3.1 Low Level
3.9.3.2 High Level
3.9.3.3 Hysteresis
B
B
C
C
USIL
USIH
∆USI
CSI
1.0
V
V
2.0
0.1
0.6
10
V
3.9.3.4 Input Capaci-
ty
pF
3.9.3.5 Input Current Pull up current source connected
to VDD
A
-ISI
10
50
µA
3.9.4 Output SO
Tristate output of the TLE6244X
(SPI output);
On active reset (RST) output SO is
in tristate.
3.9.4.1 Low Level
3.9.4.2 High Level
ISO = 2mA
A
A
USOL
0.4
V
V
I
SO = -2mA
USOH UVDD
- 1.0
3.9.4.3 Capacity
Capacity of the pin in tristate
C
A
CSO
10
10
pF
µA
3.9.4.4 Leakage Cur- In tristate
rent
ISO
-10
Final Data Sheet
59
V4.2, 2003-08-29
INFINEON [ Infineon ]
