TDA5235
Functional Description
Selection of a TSI Pattern
TSI patterns must be different to the wake-up bit stream and the RUNIN to clearly mark
the start of the following payload data frame. It should be considered that the
synchronization has a tolerance of about one bit. In addition, synchronization is related
to data chips, and may occur in the middle of a data bit. This all must be tolerated by the
data framer. Further details can be seen in Chapter 2.4.8.3 Clock and Data Recovery.
Ideal TSI patterns have a unique bit combination at their end, which may also contain a
number of code violations (CVs), when possible (see Chapter 2.4.8.4 Data Slicer and
Line Decoding).
Some examples of TSI patterns:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
When CVs are used:
0 0 0 0 0 0 0 0 0 0 0 0 0 M 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 M 0
Note: CVs in a TSI are practical for better differentiation to the real data, especially if
repetition of data frames is used for wake-up.
End of Message (EOM) Detection
An End Of Message (EOM) detection feature is provided by the EOM detector. Three
criteria can be selected to indicate EOM.
The first is based on the number of received bits since frame synchronization. The
number of expected bits is preset in the x_EOMDLEN register. Sending fewer bits as
defined in the register will result in no EOM. The EOM counter will be reset after new
frame synchronization.
In 8-Bit Parallel TSI Mode and 8-Bit Extended TSI Mode, the payload length for the two
independent TSI pattern may be different. Therefore the payload length for TSI B pattern
can be preset in the x_EOMDLENP register, while payload length for TSI A pattern can
be preset in the x_EOMDLEN register.
The second criterion is the detection of a Code Violation. This EOM criterion is not
applicable for Data Slicer Bit mode.
Data Sheet
59
V1.0, 2010-02-19
INFINEON [ Infineon ]
