TDA5235
Functional Description
steps. The 5 MSB bits (TSIGAP) define the real gap time and the 3 LSB bits
(GAPVAL) the DCO (digital controlled oscillator) phase correction value.
clock recovery phase
readjustment start point
valid data
all space or all mark
valid data
RUNIN
TSI A
TSI GAP
PLL sync
GAPSync
TSI B
< 1bit
Figure 32
Clock Recovery Gap Resynchronization Mode TSIGRSYN = 0
When the time TSI GAP in the start sequence of the transmitted telegram has elapsed,
the receiver needs a certain time (GAPSync = 5...6 chips) to readjust the PLL settings.
Behavior of the system at the starting position of the TSI B:
The starting position (TSI B start) for the TSI B comparison is independent from the
RUNIN settings (x_CDRRI register) and the resynchronization mode (x_TSIMODE
register):
TSIBstart[chips] = TSIGAP[chips] + 6…8
The incoming chips at TSI B start and the following incoming chips are compared with
the contents of the register TSI B. Please notice that the receiver’s PLL runs at the data
rate determined before the gap. Therefore, the receiver calculates the gap based on this
data rate.
Behavior of the system at the ending position of TSI B:
The system checks for the TSI B to match within a limited time. If there is no match within
this time, then the receiver starts again to search for the TSI A pattern at the following
incoming chips:
TSIBstop[chips] = TSIGAP[chips] + TSILENB[chips] + 11
For a successful TSI B pattern match, the defined TSI B pattern must be between “Start
of TSI B” and “Stop of TSI B”. In the example below, the earliest possible start position
would be the 18th chip and the latest possible start position would be the 22nd chip.
Data Sheet
61
V1.0, 2010-02-19
INFINEON [ Infineon ]
