TDA5235
Functional Description
thresholds are set so that almost all packets with a data rate error of +/-10% and larger
are rejected.
The following statements summarize some important aspects that need to be kept in
mind when using the described functionality:
• The output of the estimator must be described on statistical terms - this means that
it can not be guaranteed that all packets with a certain data rate outside the allowed
range will be rejected
• The quality of the estimated data rate value is mainly influenced by the setting of the
signal and noise detectors
• Reducing the RUNIN length in register x_CDRRI reduces the quality of the data rate
estimation, resulting in a degradation of the performance of the data rate acceptance
limitation block
• The same threshold can be used for FSK and ASK
• If the thresholds are too small it may happen that also packets with a valid data rate
are rejected
2.4.8.4 Data Slicer and Line Decoding
The output signal of the matched filter within the internal data processing path is in the
range of +x to -x (x is the maximum value of the internal bit width). If Code Violations
within a Manchester encoded bitstream have to be detected, the data slicer has to
recover the underlying chipstream instead of the bitstream. In this case zero values at
the matched filter output lead to an additional slicing threshold and an implicit sensitivity
loss. To provide the full reachable sensitivity for applications which do not need the
symbols S (space) and M (mark), the data slicer has two different operating modes:
• Chip mode (Code Violations are allowed)
• Bit mode (without Code Violations)
The chip mode introduces an implicit sensitivity loss compared to the bit mode, because
a zero-crossing in the 2-chip matched filter signal must be detectable. This is only
possible when an additional slicing level is introduced in the data slicer.
The data slicer internally maps a positive value to a 1 and a negative value to a -1.
Everything inside the zero thresholds (zero-tube) becomes a 0. After that, the decoding
to the chip-level representation is done by mapping the -1 to a "0" chip and the 1 to a "1"
chip. A zero out of the data slicer is decoded to chip-level by referencing to the previous
chip value.
Data Sheet
48
V1.0, 2010-02-19
INFINEON [ Infineon ]
