TDA5235
Functional Description
Number of Required RUNIN Bits
The number of RUNIN bits specified in x_CDRRI register should always be 3.0. This
setting defines the duration of the internal synchronization. Because of internal
processing delays, the pattern length that must be reserved for RUNIN is longer.
The ideal RUNIN pattern is a series of either Manchester 1’s or Manchester 0’s. This
pattern includes the highest number of edges that can be used for synchronization. In
this case, the number of physically sent RUNIN bits is 4.
For any other RUNIN pattern, 5.5 bits should be reserved for RUNIN.
TVWIN (Timing Violation WINdow length)
The PLL unlocks if the reference signal is lost for more than the time defined in the
x_TVWIN register. During the TSI Gap (see TSI Gap Mode in Chapter 2.4.8.6 Frame
Synchronization), the PLL and the TVWIN are frozen.
TVWIN time is the time during which the Digital Baseband Receiver should stay locked
without any incoming signal edges detected. The time resolution is T/16.
Calculation of TVWIN can be seen at the end of subsection TSI Gap Mode in
Chapter 2.4.8.6 Frame Synchronization.
Data Sheet
45
V1.0, 2010-02-19
INFINEON [ Infineon ]
