欢迎访问ic37.com |
会员登录 免费注册
发布采购

TDA5235 参数 Datasheet PDF下载

TDA5235图片预览
型号: TDA5235
PDF下载: 下载PDF文件 查看货源
内容描述: 增强灵敏度双配置接收器,具有数字基带处理 [Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing]
分类和应用:
文件页数/大小: 259 页 / 6799 K
品牌: INFINEON [ Infineon ]
 浏览型号TDA5235的Datasheet PDF文件第37页浏览型号TDA5235的Datasheet PDF文件第38页浏览型号TDA5235的Datasheet PDF文件第39页浏览型号TDA5235的Datasheet PDF文件第40页浏览型号TDA5235的Datasheet PDF文件第42页浏览型号TDA5235的Datasheet PDF文件第43页浏览型号TDA5235的Datasheet PDF文件第44页浏览型号TDA5235的Datasheet PDF文件第45页  
TDA5235  
Functional Description  
hexadecimals. For a final application the Signal Detector Threshold should be varied to  
optimize the false alarm rate and the sensitivity.  
Verification if Squelch only is possible  
Apply a bit pattern (e.g. PRBS9) with correct data rate at about -80 dBm input signal  
power and minimum FSK deviation to the RF input. Do 500 (50) readings of SPWR,  
calculate average minus three times the Standard Deviation. This value should be higher  
than the calculated Signal Detector Threshold calculated above. If this is not the case,  
Signal Detector AND Noise Detector must be used.  
Noise Detector Threshold  
Do 500 (50) readings of NPWR with no RF input signal applied (=noise only). Calculate  
average and Standard Deviation. Noise Detector Threshold is average minus the  
Standard Deviation. Round this value and convert it to hexadecimals. For a final  
application, the Noise Detector Threshold should be varied to optimize false alarm rate  
and sensitivity.  
Signal Detector Low Threshold  
The Signal Detector Low Threshold is always required in combination with the Noise  
Detector.  
Set register bit SDLORE to 1 and set bit group SDLORSEL to 00. Apply a bit pattern (e.g.  
PRBS9) at correct data rate at about -80 dBm input signal power and minimum FSK  
deviation to the RF input. Do 500 (50) readings of SPWR, calculate average. If average  
is larger than 200 dec (=0xC8), SDLORSEL has to be increased to the next larger value  
until average is smaller than 200 dec. x_SIGDETLO = 0.8 * (average - 3 * Standard  
Deviation). Set register SDLORE back to 0. The last setting of bit group SDLORSEL  
must also be used for configuration!  
Verification  
Threshold settings should be verified by testing receiver sensitivity over the input  
frequency range, with a step size of 100Hz, at minimum FSK deviation with all  
combinations of minimum and maximum data rate and duty cycle.  
Further detailed information can be taken from the corresponding Application Note.  
Data Sheet  
41  
V1.0, 2010-02-19  
 复制成功!