TC1796
Functional Description
3.18
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failure. The WDT helps to abort an accidental
malfunction of the TC1796 in a user-specified time period. When enabled, the WDT will
cause the TC1796 system to be reset if the WDT is not serviced within a user-
programmable time period. The CPU must service the WDT within this time interval to
prevent the WDT from causing a TC1796 system reset. Hence, routine service of the
WDT confirms that the system is functioning properly.
In addition to this standard “Watchdog” function, the WDT incorporates the EndInit
feature and monitors its modifications. A system-wide line is connected to the End-of-
Initialization (Endinit) feature and monitors its modifications. A system-wide line is
connected to the WDT_CON0.ENDINIT bit, serving as an additional write-protection for
critical registers (besides Supervisor Mode protection)
A further enhancement in the TC1796’s WDT is its reset pre-warning operation. Instead
of immediately resetting the device on the detection of an error (the way that standard
Watchdogs do), the WDT first issues an Non-Maskable Interrupt (NMI) to the CPU
before finally resetting the device at a specified time period later. This gives the CPU a
chance to save system state to memory for later examination of the cause of the
malfunction, an important aid in debugging.
Features
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16-bit Watchdog counter
Selectable input frequency: fSYS/256 or fSYS/16384
16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Pre-warning Modes
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Incorporation of the ENDINIT bit and monitoring of its modifications
Sophisticated password access mechanism with fixed and user-definable password
fields
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Proper access always requires two write accesses. The time between the two
accesses is monitored by the WDT and limited.
Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation.
Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation.
Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled.
Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system
malfunction is assumed and the TC1796 is held in reset until a power-on reset. This
prevents the device from being periodically reset if, for instance, connection to the
external memory has been lost such that even system initialization could not be
performed
Data Sheet
69
V1.0, 2008-04
INFINEON [ Infineon ]
