TC1796
Functional Description
3.14.1
Functionality of GPTA0/GPTA1
Each of the General Purpose Timer Arrays (GPTA0 and GPTA1) provides a set of
hardware modules required for high speed digital signal processing:
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Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
Phase Discrimination Logic units (PDL) decode the direction information output by a
rotation tracking system.
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Duty Cycle Measurement Cells (DCM) provide pulse-width measurement
capabilities.
A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA
module clock ticks during an input signal’s period.
Global Timer units (GT) driven by various clock sources are implemented to operate
as a time base for the associated Global Timer Cells.
Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an external or internal event. A GTC may be also used to control an external
port pin depending on the result of an internal compare operation. GTCs can be
logically concatenated to provide a common external port pin with a complex signal
waveform.
Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may be also
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or
triggered by various external or internal events.
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Input lines can be shared by an LTC and a GTC to trigger their programmed operation
simultaneously.
The following sections summarize the specific features of the GPTA units. The clock
signal fGPTA is the input clock of the GPTA modules (max. 75 MHz in TC1796).
Clock Generation Unit
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Filter and Prescaler Cell (FPC)
– Six independent units
– Three basic operating modes:
Prescaler, Delayed Debounce Filter, Immediate Debounce Filter
– Selectable input sources:
Port lines, GPTA module clock, FPC output of preceding FPC cell
– Selectable input clocks:
GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or
uncompensated PLL clock.
– fGPTA/2 maximum input signal frequency in Filter Modes
Phase Discriminator Logic (PDL)
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– Two independent units
– Two operating modes (2 and 3 sensor signals)
Data Sheet
60
V1.0, 2008-04
INFINEON [ Infineon ]
