TC39x BC/BD-Step
Pin Definition and Functions: LFBGA-516 Package Variant Pin Configuration
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J17
P14.9
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM3_IN3_3
GTM_TIM2_IN3_3
ASCLIN0_ACTSA
QSPI2_MRSTFN
ASCLIN9_ARXD
P14.9
Mux input channel 3 of TIM module 3
PU1 /
VEXT /
ES
Mux input channel 3 of TIM module 2
Clear to send input
Master SPI data input (LVDS N line)
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT89
CAN23_TXD
MSC0_EN1
CAN transmit output node 3
Chip Select
CAN10_TXD
ERAY0_TXENB
ERAY0_TXENA
ERAY1_TXENA
P14.10
CAN transmit output node 0
Transmit Enable Channel B
Transmit Enable Channel A
Transmit Enable Channel A
J16
LVDS_R General-purpose input
X / FAST /
GTM_TIM3_IN4_3
GTM_TIM2_IN4_3
CAN23_RXDA
QSPI2_MRSTFP
P14.10
Mux input channel 4 of TIM module 3
PU1 /
VEXT /
ES
Mux input channel 4 of TIM module 2
CAN receive input node 3
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
GTM_TOUT90
QSPI5_SCLK
MSC0_EN0
Master SPI clock output
Chip Select
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDA
ERAY1_TXDA
Transmit output
Monitor input 2
Reference input 2
O5
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Transmit Channel A
Transmit Channel A
Data Sheet
78
V 1.2, 2021-03
OPEN MARKET VERSION