TC39x BC/BD-Step
Pin Definition and Functions: LFBGA-516 Package Variant Pin Configuration
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F20
P14.1
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
GTM_TIM1_IN4_3
GTM_TIM0_IN4_3
ERAY0_RXDA3
ASCLIN0_ARXA
SENT_SENT18D
ERAY0_RXDB3
CAN01_RXDB
SCU_E_REQ3_1
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive Channel A3
Receive input
Receive input channel 18
Receive Channel B3
CAN receive input node 1
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
PMS_PINAWKP
P14.1
PINA ( P14.1) pin input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT81
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P14.2
T13 PWM channel 63
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
HWCFG2 pin input
General-purpose output
GTM muxed output
Transmit output
K18
I
SLOW /
PU2 /
VEXT /
ES
GTM_TIM1_IN5_3
GTM_TIM0_IN5_3
PMS_HWCFG2IN
P14.2
O0
O1
O2
GTM_TOUT82
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO1
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
—
Reserved
ASCLIN2_ASCLK
—
Shift clock output
Reserved
Data Sheet
74
V 1.2, 2021-03
OPEN MARKET VERSION