TC1767
Introduction
Analog Input
Stages
Channel Amplifier
Stages
Converter Stage
V
DDMF
FAIN0P
FAIN0N
Rp
conversion
control
A/D
Control
Rn
gain
VSSMF
CHNR
Rp
Rn
V
DDMF
FAIN2P
FAIN2N
V
SSMF
A/D
Rp
Rn
V
DDMF
FAIN1P
FAIN1N
V
DDAF
V
SSAF
VSSMF
Rp
Rn
V
DDMF
FAIN3P
FAIN3N
VSSMF
MCA06432_m4n
V
DDIF
VSSMF
Figure 14
2.5
FADC Input Structure in TC1767
On-Chip Debug Support (OCDS)
The TC1767 contains resources for different kinds of “debugging”, covering needs from
software development to real-time-tuning. These resources are either embedded in
specific modules (e.g. breakpoint logic of the TriCore) or part of a central peripheral
(known as CERBERUS).
2.5.1
On-Chip Debug Support
The classic software debug approach (start/stop, single-stepping) is supported by
several features labelled “OCDS Level 1”:
• Run/stop and single-step execution independently for TriCore and PCP.
• Means to request all kinds of reset without usage of sideband pins.
• Halt-after-Reset for repeatable debug sessions.
Data Sheet
49
V1.3, 2009-09
INFINEON [ Infineon ]
