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SAB82526N 参数 Datasheet PDF下载

SAB82526N图片预览
型号: SAB82526N
PDF下载: 下载PDF文件 查看货源
内容描述: 数据通信芯片 [Data Communications ICs]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路数据通信数据传输时钟
文件页数/大小: 126 页 / 720 K
品牌: INFINEON [ Infineon ]
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SAB 82525  
SAB 82526  
SAF 82525  
SAF 82526  
The following figure gives an example of a DMA driven transmission sequence with a  
supposed frame length of 70 bytes, i.e. programmed transmit byte count (XCNT) equal  
69 bytes.  
Transmit Frame (70 Bytes)  
32  
32  
6
Serial  
Interface  
HSCX  
(69)  
CPU/DMA  
Interface  
DRQT(32)  
DRQT(32)  
DRQT(6)  
. . .  
. . .  
. . .  
WR  
WR  
WR  
WR  
WR  
WR  
WR XTF  
XCNT  
XPR  
DMA Write Cycles (70)  
ITD00250  
Figure 36  
DMA Driven Transmission Sequence Example  
7.5 Data Reception  
Interrupt Mode  
Also 2×32 byte FIFO buffers (receive pools) are provided for each channel in receive direction.  
There are two different interrupt indications concerned with the reception of data:  
– RPF (Receive Pool Full) interrupt, indicating that a 32 byte block of data can be read from  
the RFIFO and the received message is not yet complete.  
– RME (Receive Message End) interrupt, indicating that the reception of one message is  
completed, i.e. either  
one message with less than 32 bytes, or the  
last part of a message with more than 32 bytes  
is stored in the RFIFO.  
After an interrupt has been processed, i.e. the received data has been read from the RFIFO,  
this must be explicitly acknowledged by the CPU issuing a RMC (Receive Message Complete)  
command.  
The CPU has to handle the RPF interrupt before additional 32 bytes are received via the serial  
interface which would cause a "Receive Data Overflow" condition.  
Semiconductor Group  
75  
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