PEB 2091
PEF 2091
Application Hints
7.4.3
Tests in Master-Reset Mode
The master-reset test mode is used for the return-loss measurements.
The master-reset mode characterizes the mode where the IEC-Q does not transmit any
signals. The chip is in the “Test" state. All echo canceller and equalizer coefficients are
reset. As can be seen from the state diagram, no activation is possible in LT or NT modes
when the device is in the “Test" state.
For measurements two methods are recommended in order to transfer the IEC-Q into
the master-reset mode:
– hardware selection:
– software selection:
RESQ = 0 & TSP = 0
C/I = RES (0001B)
The C/I-code transmitted by the IEC-Q in the “Test" state is DEAC in LT modes and DR
in all NT modes.
Return-Loss Measurement
– Return loss is defined in ANSI T1.601 and ETSI TS 101080
– IEC-Q is in Test state
– Measure complex impedance “Z" from 14 kHz – 200 kHz
– Calculate return loss with formula:
RL(dB) = 20log (abs((Z + 135) / (Z –135)))
Quiet Mode Measurement
– Quite mode is defined in ANSI T1.601
– IEC-Q is in the Test state
– Trigger and exit criteria have to be realized externally
Semiconductor Group
261
Data Sheet 01.99
INFINEON [ Infineon ]
