PEB 2091
PEF 2091
Operational Description
DR
SL0/SP
Test
SL0
-
-
Deactivated
DI
TN & DC
ARL
T2E
Any State
Pin-SSP or
Pin-RES or
Pin (PS1=1) or
µP-SSP or
µP-RES or
SSP or RES or
PFOFF or LTD
HI
DEAC
(AR or AR0 or
ARX or UAR) &
/TN
T1S,
T2S
RES or
RES1
Pin PS1=1
T1S, T2S
TL
SL0
-
-
T2S
Alerting
DI
Reset for Loop
DI
T2E
T3S
T2S
T3E
SL0
-
RES1
Wait for TN
DI
EI3
T1E
T1S, T4S
Legend
TN or TL
(Loop)
IN
T1S
T9S,
T4S
SL0
SL0
Signal to U
SB to U
-
-
Awake
AR
LSEC or
T4E
SL1
Awake Error
AR
State Name
T1S
T9E &
CI-Code Indication (DU)
T9E &
/(LSEC or T4E)
T5S
(LSEC or T4E)
OUT
-
T1S, T5S
EC-Training
AR
(AR or ARL) & (LSEC or T5E)
T6S
SL2
-
EC-Converged
ARM
SEC or T6E or ARL
SL2
EQ-Training
EI3 ARM
-
RES1
SFD & (BBD1 or BBD0 or CRCOK)
T1E
T8S
LSUE
LSUE
DR
SL3T
-
Pend. Transparent
UAI/FJ
LOF
T8E
SL3T
-
DR
Transparent
A//FJ
EI2/FJ
Any State
Pin-DT, µP-DT
or DT
LOF
T10S
SL3T
SL3T
SL3T
-
-
-
Loss of Signal
LSL
Loss of Synchr.
RSY
Pend. Deactivation
DEAC
RES1
T10E
RES1
T7S
SL0
SL0
SL0
-
-
-
LSU
LSU
T7S
Receiver Reset
LSL
Tear Down Error
EI3/RSY
Tear Down
DEAC
TN
T7E
Figure 75
State Transition Diagram LT-Repeater Mode
Semiconductor Group
174
Data Sheet 01.99
INFINEON [ Infineon ]
