PEB 2091
PEF 2091
Operational Description
Pending Alerting 1
Note 46: This state only exists in NT-Auto Activation mode.
The "Pending Alerting" state is entered upon detection of loss of framing on the
U-interface or expiry of timer T1. This failure condition is signalled to the LT side by
turning off the transmit level (SN0). The IEC-Q then waits for a response (no signal level
LSU) from the LT side to enter the "Alerting 1" state.
Pending Timing
The pending timing state assures that the C/I-channel code DC is issued four times
before the timing signals on the IOM®-2 interface are turned off.
In case the NT-Auto Activation mode is selected the recognition of the LT wake-up tone
TL is assumed every time the "Pending Timing" state has been entered from the "Test"
state. This function guarantees that the NT (in NT-Auto Activation mode) starts one
activation attempts after having been reset, see "Activation Attempt Initiated by NT in
NT-Auto Activation Mode", page 142.
Receive Reset
The "Receive Reset" state is entered upon detection of a deactivation request from the
LT side, after a failure condition on the U-interface (loss of signal level LSUE), or
following the "Pending Reset" state upon expiry of timer T1 or loss of framing. No signal
is transmitted on the U-interface, especially no wake-up signal TN, and the S-transceiver
or microcontroller is requested to start the deactivation procedure on the NT side (DR).
Timer T7 assures that no activation procedure is started from the NT side for a minimum
period of T7. This gives the LT a chance to activate the NT.
The state is left only after completion of the deactivation procedure on the NT side
(receipt of the C/I-channel code DI), unless a wake-up tone is received from the LT side.
Synchronized 1
When reaching this state the IEC-Q informs the LT side by sending the superframe
indication (inverted synchronization word). The loop-back commands decoded by the
EOC-processor control the output of the transmit signals:
– Normal activation and UOA = 0:
SN3
– Any loop-back and UOA = 0 (no loop-back):
SN3T
The value of the issued SAI-bit depends on the received C/I-channel code: DI and TIM
lead to SAI = 0, any other C/I-code sets the SAI-bit to 1 indicating activity on the
S/T-interface. The IEC-Q waits for the receipt of UOA = 1 to enter the "Synchronized 2"
state.
Semiconductor Group
171
Data Sheet 01.99
INFINEON [ Infineon ]
