PEB 2091
PEF 2091
Operational Description
EQ-Training
The Receiver waits for signal SL1 or SL2 to be able to update the AGC, to recover the
timing phase, to detect the synch-word (SW), and to update the EQ-coefficients. The
"EQ-training" state is left upon detection of binary "0s" in the B- and D-channels for a
period of 6–12 ms corresponding to the detection of SL2.
Error S/T
Loss of framing or loss of incoming signal has been detected on the S/T-interface (EI1).
The LT side is informed by setting the ACT-bit to "0" (loss of transparency on the NT
side). The following codes are issued on the C/I-channel:
– Normal activation or single-channel loop-back:
– Loop-back 2:
AR
ARL
IOM®-2 Awaked
Timing signals are delivered on the IOM®-2 interface. The IEC-Q enters the
"Deactivated" state again upon detection of the C/I-channel code DI (idle code).
Pending Deactivation of S/T
The IEC-Q has received the UOA-bit at zero after a complete activation of the
S/T-interface. The IEC-Q deactivates the S/T-interface by issuing DR in the C/I-channel.
The value of the ACT-bit depends on its value in the previous state.
Pending Deactivation of U-Interface
The IEC-Q waits for the receive signal level to be turned off (LSU) to enter the "Receiver
Reset" state and start the deactivation procedure.
Pending Receive Reset
Note 45: This state doesn’t exist in NT-Auto Activation mode.
The "Pending Receive Reset" state is entered upon detection of loss of framing on the
U-interface or expiry of timer T1. This failure condition is signalled to the LT side by
turning off the transmit level (SN0). The IEC-Q then waits for a response (no signal level
LSU) from the LT side to enter the "Receive Reset" state.
Semiconductor Group
170
Data Sheet 01.99
INFINEON [ Infineon ]
