Functional Description
2.5.1
S/T Interface
According to CCITT recommendation I.430 pseudo-ternary encoding with 100% pulse width is
used on the S/T interface. A logical "1" corresponds to a neutral level (no current), whereas
logical "0" ’s are encoded as alternating positive and negative pulses. An example is shown in
figure 42.
0
1
0
0
1
1
0
0
0
1
1
+ V
0 V
- V
ITD00322
Figure 42
S/T Interface Line Code
One frame consists of 48 bits, at a nominal bit rate of 192 kbit/s. Thus each frame carries two
octets of B1, two octets of B2, and four D-bits, according to the B1+B2+D structure defined for
the ISDN basic access (total useful data rate: 144 kbit/s). Frame begin is marked using a code
violation (no Mark inversion). The frame structures (from network to subscriber, and subscriber
to network) are shown in figure 43.
48 Bits in 250 µs
DL. FL.
B1
E D A FA N
B2
E D M
B1
E D S
B2
E D L. F L.
0
1
0
NT
TE
2 Bits Offset
DL. FL.
B1
L.D L.FA L.
B2
L.D L.
B1
L.D L.
B2
L.D L. F L.
0
1
0
TE
NT
t
F = Framing Bit
L = DC Balancing Bit
D = D-Channel Bit
E = D-Echo-Channel Bit
FA = Auxiliary Framing Bit or Q-Bit
N = Bit set to a Binary Value N= FA
B1 = Bit within B Channel 1
B2 = Bit within B Channel 2
A = Bit used for Activation
S = Subchannel SC1 through SC5 bit position
M = Multiframing Bit
ITD02330
Figure 43
Frame Structure at Reference Points S and T (CCITT I.430)
Note: Dots demarcate those parts of the frame that are independently DC-balanced.
Semiconductor Group
81
INFINEON [ Infineon ]
