Functional Description
The right-hand side consists of:
– the serial interface logic for the IOM and the SLD and SSI interfaces, with B-channel
switching capabilities
– the logic necessary to handle the D-channel messages (layer 2).
The latter consists of an HDLC receiver and an HDLC transmitter together with 64-byte deep
FIFO's for efficient transfer of the messages to/from the user's CPU.
In a special HDLC controller operating mode, the auto mode, the ISAC-S processes protocol
handshakes (I- and S-frames) of the LAPD (Link Access Procedure on the D channel)
autonomously.
Control and monitor functions as well as data transfers between the user's CPU and the D and
B channels are performed by the 8-bit parallel µP interface logic.
The IOM interface allows interaction between layer-1 and layer-2 functions. It implements D-
channel collision resolution for connecting other layer-2 devices to the IOM interface (TIC bus),
and the C/I and MONITOR channel protocols (IOM-1/IOM-2) to control peripheral devices.
The timing unit is responsible for the system clock and frame synchronization.
2.2
Interface and Operating Modes
The ISAC-S is configurable for the following applications:
– ISDN terminals
→
→
→
→
TE mode
– ISDN subscriber line termination
– ISDN network termination
LT-S mode
NT mode
LT-T mode
– ISDN trunk line termination
(PABX connection to Central Office)
Configuration is performed by pin-strapping (pins M1, M0), yielding different meanings to the
multifunctional pins (X0 (PEB 2085 only), X1, X2) as well as the clock and framing signal pins
(DCL, FSC1, FSC2, CP) see table 1 and 2.
Two basic modes are distinguished, according to whether the ISAC-S is programmed to
operate with the IOM-1 or with the IOM-2 interface. This programming is performed via bit IMS
in the ADF2 register.
2.2.1
IOM®-1 Interface Mode (ADF2:IMS=0)
In this mode the IOM-1 interface is primarily used to interconnect the layer-1 and layer-2 parts
inside the ISAC-S. B-channel interfacing is performed via the auxiliary serial SSI and SLD
interfaces.
The external availability of the IOM interface ports (IDP0, 1) can be used for TIC bus
applications (several layer-2 devices occupying the same D and Command/Indicate channel
connected to one layer-1 device).
The Timing Mode (SPCR:SPM) defines the operating mode of the SLD interface (master/
slave) and the phase relationship between the SLD and IOM interface (see chapter 2.3.1).
The operating modes are shown in table 1.
Semiconductor Group
32
INFINEON [ Infineon ]
