Functional Description
2
Functional Description
2.1
General Functions and Device Architecture
The functional block diagram of the ISAC-S is shown in figure 10.
The left-hand side of the diagram contains the layer-1 functions, according to CCITT I series
recommendations:
– S-bus transmitter and receiver
– timing recovery and synchronization by means of digital PLL circuitry
– activation/deactivation
– access to S and Q channels
– handling of D channel
– test loops
– send single/continuous AMI pulses (diagnostics).
M1 M0
Buffer
IDP1 IDP0
SX1
SX2
SDAR
AMI
BIN
SSI Port
SLD Port
SDAX/
SDS1
SIP/EAW
R
IOM
Interface
HDLC
HDLC
LAPD
Controller
Status
Command
Register
Receiver Transmitter
D-CH
Access
VSSA
Control
FIFO
Controller
R-FIFO
X-FIFO
*
UFI
VDD
SR2
SR1
AMI
Buffer
BIN
VSSD
*
XTAL1
XTAL2
Timing
RST
DPLL
µP-Interface
*
X0, X1, X2
CP/BCL DCL
FSC1 FSC2 SCA/ AD0-AD7/
FSD/ A0-A5&
Control
INT
ITB00850
*
Only PEB 2085
SDS2
D0-D7
Figure 10
Architecture of the ISAC®-S
Semiconductor Group
31
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