Low Level Controller
}
else
if (pt->pt_rx_cnt > 266)
pt->pt_rx_frame = PT_FR_OVERFLOW;
/* read the bytes from the RFIFO
/* if no error was detected
*/
*/
if (pt->pt_rx_frame < PT_FR_ERROR)
{
if (RecCnt)
{
STRING_IN (pt->pt_rx_curr, pt->pt_r_fifo, RecCnt);
pt->pt_rx_curr += RecCnt;
/* update buffer pointer
/* it points to the next free
/* location in the buffer
*/
*/
*/
}
}
if (rpf)
{
/* return when it was a RPF int.
*/
outp (pt->pt_r_cmdr, CMDR_RMC | (inp (pt->pt_r_star) & CMDR_RNR));
return;
}
/* RME interrupt handling !!!
/* ==========================
*/
*/
/* the receive status byte is in
/* register RSTA
*/
*/
rsta = inp (pt->pt_r_rsta);
/************************************************************************/
/* It follows a scanning section to get some information about the
/* received data:
/* - Performed address recognition
*/
*/
*/
*/
*/
*/
*/
/* - SAPI (’sapi’), TEI (’tei’) and control field byte(s) (’ctrl’)
/*
/*
as well as the type of frame (HDLC U, UI, S or I frame) are
determined.
/* In addition the length of a frame is checked.
/************************************************************************/
/* set ’pei’ according to performed */
/* address recognition
|= ((rsta & 0x0C) >> 1) | (rsta & 0x01);
= FALSE;
*/
*/
pei
AutoM
tei
sapi
ptr
= 0;
= rsta & 0x02;
= pt->pt_rx_start;
/* get the C/R bit value
/* now get additional information
/* (TEI, SAPI, control field)
/* It depends on the selected
/* operating mode
*/
*/
*/
*/
switch (pt->pt_op_mode)
{
case PT_MD_CLEAR_EXT:
/* no address recognition,
/* no firmware interaction
*/
*/
Semiconductor Group
302
INFINEON [ Infineon ]
