Low Level Controller
{
case PT_FR_FAULT:
if (rsta & RSTA_RDO)
REC_DATA_OVERFLOW (pei);
if (rsta & RSTA_RAB)
REC_ABORTED (pei);
if (rsta & RSTA_CRC)
CRC_ERROR (pei);
/* CRC has already been inverted
*/
break;
case PT_FR_S:
/* HDLC S frame ?
/* ==============
/* extra parameter for 1 byte
/* address field set to FALSE
*/
*/
*/
*/
Decode_S_Frame_BASIC (pei, sapi, tei, ctrl, frame_status,
((pt->pt_state & PT_M128) ? 0x01 : 0x00), FALSE);
MMU_free (pt->pt_rx_start);
break;
case PT_FR_U:
/* HDLC U frame ?
/* ==============
/* extra parameter for 1 byte
/* address field set to FALSE
*/
*/
*/
*/
Decode_U_Frame_BASIC (pei, sapi, tei, (BYTE) ctrl, FALSE);
MMU_free (pt->pt_rx_start);
break;
case PT_FR_UI:
case PT_FR_I:
case PT_FR_TR:
/* HDLC UI or I frame ?
/* ====================
/* ====================
*/
*/
*/
if (pt->pt_rx_frame < PT_FR_ERROR)
{
FRAME_PASS
fp;
fp.mmu_buff
= pt->pt_rx_start;
fp.start_of_i_data
fp.i_data_cnt
fp.Two_byte_cf
fp.ctrl_field
fp.pei
= ptr;
= pt->pt_rx_cnt;
= Two;
= ctrl;
= pei;
fp.frame
= pt->pt_rx_frame | frame_status;
fp.sapi
fp.tei
= sapi;
= tei;
/* transfer the frame to the ’long */
/* frame queue’ */
PassLongFrame_BASIC (&fp);
}
break;
/* end of ’switch (pt->pt_rx_frame)’ ------------------------------- */
}
Semiconductor Group
306
INFINEON [ Infineon ]
