Low Level Controller
if (ista & ISTA_RSC)
{
if (inp (pt->pt_r_star) & 0x10)
PEER_REC_BUSY (pt->pt_pei);
else
/* peer receiver busy
*/
PEER_REC_READY (pt->pt_pei); /* peer receiver ready
*/
}
/* B (2.x) versions of L1 device
*/
/* controllers can’t prevent CIC bit*/
/* being set even when masked. */
/* CIC interrupt ? (layer 1 device */
/* status change) */
if ((ista & ISTA_CIC) && !interrupt_act)
IntLay1_BASIC (pt);
if (ista & ISTA_EXI)
{
/* Extended interrupt ?
/* ==================
/* transmit message repeat int. ?
*/
*/
*/
if ((exir & EXIR_XMR) && !(exir & EXIR_PCE) && !(ista & ISTA_TIN))
{
XMR_ERROR (pt->pt_pei);
FREE_TX_PATH (pt->pt_pei);
}
if (exir & EXIR_XDU)
/* transmit data underrun ?
*/
{
TX_DATA_UNDERRUN (pt->pt_pei);
FREE_TX_PATH (pt->pt_pei);
}
if (exir & EXIR_PCE)
{
/* protocol error interrupt ?
/* ResetHDLC_ICC (pt->pt_pei);
*/
*/
PROTOCOL_ERROR (pt->pt_pei);
}
if (exir & EXIR_RFO)
/* receive frame overflow int. ?
*/
{
MMU_free (pt->pt_rx_start);
pt->pt_rx_start
pt->pt_state
= NULL_PTR;
&= ~PT_REC_ACTIVE;
pt->pt_rx_frame
pt->pt_rx_cnt
= 0;
= 0;
REC_FRAME_OVERFLOW (pt->pt_pei);
}
if (exir & EXIR_MOR)
if (interrupt_act)
IntMon_MOFC ();
else
/* MON channel interrupt ?
*/
Wr_IntMon_MOFC ();
Semiconductor Group
299
INFINEON [ Infineon ]
