Low Level Controller
{
/* *******************
*/
case PT_MD_AUTO:
mode_reg
/* HDLC AUTO MODE
*/
*/
*/
*/
*/
/* full address recognition,
/* internal timer mode, receiver
/* active, 2 bytes address fields
/* are selected.
|= (MODE_TMD | MODE_RAC | MODE_ADM);
outp (pt->pt_r_timr, tim_mode);
break;
case PT_MD_NON_AUTO:
/* HDLC NON AUTO MODE
/* full address recognition,
*/
*/
/* receiver active, 2 byte address */
/* fields
|= (MODE_MDS0 | MODE_RAC | MODE_ADM);
*/
mode_reg
if (((pt->pt_op_mode == PT_MD_AUTO) &&
(pt->pt_state & PT_TX_ACTIVE) && (pt->pt_tx_frame == PT_FR_I))
|| (inp(pt->pt_r_star2) & (STAR2_TREC | STAR2_WFA)))
{
MISSING_ACKNOWLEDGE (pei);
ResetHDLC_ICC (pei);
}
outp (pt->pt_r_timr, 0);
break;
case PT_MD_TRANSP:
/* TRANSPARENT MODE
/* SAPI-address (high-byte)
/* recognition
*/
*/
*/
mode_reg
break;
|= (MODE_MDS1 | MODE_MDS0 | MODE_RAC | MODE_ADM);
case PT_MD_EXT_TRANSP:
case PT_MD_CLEAR_EXT:
/* EXTENDED TRANSPARENT MODE
/* as well as clear mode
/* no address recognition
*/
*/
*/
mode_reg
break;
|= (MODE_MDS1 | MODE_MDS0 | MODE_RAC);
default:
outp (pt->pt_r_mask, 0x00);
return (ACK_WRONG_PARM);
}
pt->pt_op_mode = mode;
/* save MODE register settings
*/
*/
/* modulo: 1 (mod 128); 0 (mod 8)
outp (pt->pt_r_sap2, (BYTE) (modulo ? 0x02 : 0x00));
outp (pt->pt_r_tei2, 0xFF);
if (modulo)
pt->pt_state |= PT_M128;
else
pt->pt_state &= ~PT_M128;
outp (pt->pt_r_mode, mode_reg);
Semiconductor Group
289
INFINEON [ Infineon ]
