Low Level Controller
pt->pt_device = PT_ISAC_S_B;
}
pt->pt_io_base = base;
/* store the base (IO) address
*/
/* the following structure
/* elements store the register IO
*/
*/
/* addresses (e.g. for FIFOs, ISTA, */
/* MASK, etc.)
*/
pt->pt_r_fifo = base + ICC_FIFO;
pt->pt_r_ista = base + ICC_ISTA;
pt->pt_r_mask = base + ICC_MASK;
pt->pt_r_star = base + ICC_STAR;
pt->pt_r_cmdr = base + ICC_CMDR;
pt->pt_r_mode = base + ICC_MODE;
pt->pt_r_timr = base + ICC_TIMR;
pt->pt_r_exir = base + ICC_EXIR;
pt->pt_r_xad1 = base + ICC_XAD1;
pt->pt_r_xad2 = base + ICC_XAD2;
pt->pt_r_sap1 = base + ICC_SAP1;
pt->pt_r_sap2 = base + ICC_SAP2;
pt->pt_r_rsta = base + ICC_RSTA;
pt->pt_r_tei1 = base + ICC_TEI1;
pt->pt_r_tei2 = base + ICC_TEI2;
pt->pt_r_rhcr = base + ICC_RHCR;
pt->pt_r_spcr = base + ICC_SPCR;
pt->pt_r_stcr = base + ICC_STCR;
pt->pt_r_cixr = base + ICC_CIXR;
pt->pt_r_monr = base + ICC_MONR;
pt->pt_r_adfr = base + ICC_ADFR;
/* = CIX0/CIR0 in later versions
/* = MOX0/MOR0 in later versions
/* = ADF1 in later versions
*/
*/
*/
pt->pt_r_rbcl = base + ICC_RFBC;
pt->pt_r_rbch = base + ICC_RBCH;
pt->pt_r_mox1 = base + ICC_MOX1;
pt->pt_r_mocr = base + ICC_MOCR;
pt->pt_r_cix1 = base + ICC_CIX1;
pt->pt_r_adf2 = base + ICC_ADF2;
/* = RBCL in later version
*/
/* = MOSR (read access)
/* CIX1 and CIR1 register
*/
*/
pt->pt_r_rfbc = base + ICC_RFBC;
pt->pt_r_sfcr = base + ICC_SFCR;
pt->pt_r_sscx = base + ICC_SSGX;
pt->pt_r_sqxr = base + ISAC_SQXR; /* S/Q channel transmit and
/* receive register
*/
*/
/* STAR2 register
*/
pt->pt_r_star2 = base + ICC_STR2;
DISABLE_TREC_STATUS_CHECK ();
}
/***************************************************************************/
/*
/*
/*
/*
*/
*/
*/
*/
Function : InitLay2_ICC ()
Parameters:
Semiconductor Group
287
INFINEON [ Infineon ]
