Functional Description
LT-S/NT mode:
– Generation of the F
A
and M bit patterns according to table 7.
bit position in frames 1, 6, 11 and 16 (Q bits) are stored as
– The four bits received in the F
A
SQR1 to SQR4 in the SQRR register. A change in any of the received bits (SQR1 or 2 or 3
or 4) is indicated by interrupt (CISQ in ISTA).
– The four bits SQX1 to SQX4 stored in the SQXR register are transmitted as the four S bits
in frames 1, 6, 11 and 16, respectively.
– The S/T multiframe generation can be disabled in the STAR2 register (MULT bit).
Table 7
S and Q Bit Position Identification and Multiframe Structure
S and Q Channel Structure
Frame Number
NT-to-TE
bit
NT-to-TE
M Bit
NT-to-TE
S Bit
TE-to-NT
bit
F
A
F
A
Position
Position
1
2
3
4
5
ONE
ONE
S1
Q1
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
6
7
8
9
10
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
S2
Q2
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
11
12
13
14
15
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
S3
Q3
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
16
17
18
19
20
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
S4
Q4
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
1
ONE
ONE
S1
Q1
2
ZERO
ZERO
ZERO
ZERO
etc.
Semiconductor Group
101
INFINEON [ Infineon ]
