Functional Description
1 → A reset signal is generated as a result of the expiration of the watchdog timer
(indicated by the WOV interrupt status).
Note that the watchdog timer is not running when the ISAC-S is in the power-down
state (IOM not clocked).
Note: Bit RSS has a significance only if terminal specific functions are activated (TSF=1).
The RSS bit should be set to "1" by the user when the ISAC-S is in power-up to prevent an
edge on the EAW line or a change in the C/I code from generating a reset pulse.
Switching RSS from 0 to 1 or from 1 to 0 resets the watchdog timer.
The reset pulse generated by the ISAC-S (output via RST pin) has a pulse width of:
– 125 µs when generated by the watchdog timer
– 16 ms when generated by EAW line or C/I code change.
Semiconductor Group
105
INFINEON [ Infineon ]
