Functional Description
Device
Settings
m = 4
Result
Fail
Comments
PEB 2085 V2.3
PEB 2086 V1.1
m = 5 or 6
Pass
2.5.7
D-Channel Access
Depending on the application, the D channel is either switched transparently (no collision
resolution) from the IOM to the S/T interface (LT-S and NT modes) or it is submitted to the D-
channel access procedure according to CCITT recommendation I.430 (TE mode). For trunk
line applications (LT-T mode) both modes of D-channel processing are applicable and may be
selected by appropriate register programming of the ISAC-S.
The D-channel access procedure according to CCITT I.430 including priority management is
fully implemented in the ISAC-S:
In TE and LT-T mode, if collision detection is programmed (MODE:DIM2-0), a collision is
detected if either an echo bit of "0" is recognized and a D bit of "1" was generated, or an echo
bit of "1" is recognized and a D bit of "0" was generated. When this occurs, D-channel
transmission is immediately stopped, and the echo channel is monitored to enable a
subsequent D-channel access to be attempted.
When used in LT-S (NT) mode the device generates the echo bits necessary for D-channel
collision detection.
Stop/Go Bit
As the collision resolution is performed by the layer-1 part of the device, an information about
the D-channel status ("ready" or "busy") must be sent back to the layer-2 part to control HDLC
transmission. For this goal a Stop/Go (S/G) bit is transmitted over the IOM interface to the
layer-2 device.
Depending on the selected IOM mode the S/G bit is either transmitted in bit 20 of an IOM-1
frame (4-byte frame structure) or in bit 90 of an IOM-2 frame (12-byte structure) (see
figures 26 and 40).
A logical "1" of the S/G bit indicates a collision on the S bus. By sending the S/G bit a logical
"0" to the layer-2 controller in anticipation of the S bus D channel "ready"-state, the first valid
0 bits will emerge from the layer-1 part at exactly that moment an access is becoming possible.
Selection of D-Channel Access Mode
For proper operation of the D-channel access procedure, the ISAC-S must be programmed via
the MODE (see chapter 4.1.7) register to evaluate the Stop/Go bit. This is achieved by setting
Semiconductor Group
98
INFINEON [ Infineon ]
