F3 PWM controller
ICE3BS03LJG
Functional Description
to the line variations. The current waveform slope will
change with the line variation, which controls the duty
cycle.
The external RSense allows an individual adjustment of
the maximum source current of the external power
MOSFET.
VOSC
max.
Duty Cycle
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
maximum duty cycle limitation the switch T2 is closed
by VOSC. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by
the inverted VOSC signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing VFB below that
threshold.
t
Voltage Ramp
0.6V
FB
t
Gate Driver
156ns time delay
t
Figure 7
Light Load Conditions
Soft-Start Comparator
PWM Comparator
3.3.1
PWM-OP
FB
The input of the PWM-OP is applied over the internal
C8
leading edge blanking to the external sense resistor
R
Sense connected to pin CS. RSense converts the source
PWM-Latch
Oscillator
current into a sense voltage. The sense voltage is
amplified with a gain of 3.2 by PWM OP. The output of
the PWM-OP is connected to the voltage source V1.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
Figure 6).
VOSC
time delay
circuit (156ns)
Gate Driver
0.6V
10kΩ
3.3.2
PWM-Comparator
X3.2
The PWM-Comparator compares the sensed current
signal of the external power MOSFET with the
feedback signal VFB (see Figure 8). VFB is created by an
external optocoupler or external transistor in
combination with the internal pull-up resistor RFB and
provides the load information of the feedback circuitry.
When the amplified current signal of the external power
MOSFET exceeds the signal VFB the PWM-
Comparator switches off the Gate Driver.
R1
T2
V1
PWM OP
C1
Voltage Ramp
Figure 6
Improved Current Mode
Version 2.0
9
6 Dec 2007
INFINEON [ Infineon ]
