F3 PWM controller
ICE3BS03LJG
Functional Description
Start block. Then the switching frequency is varied in Thus the leading switch on spike is minimized.
range of 65KHz ± 2.6KHz at period of 4ms.
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage.
During power up, when VCC is below the undervoltage
lockout threshold VVCCoff, the output of the Gate Driver
is set to low in order to disable power transfer to the
secondary side.
3.5.2
PWM-Latch FF
The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the external
power MOSFET. After the PWM-Latch is set, it is reset
by the PWM comparator, the Soft Start comparator or
the Current -Limit comparator. When it is in reset mode,
the output of the gate driver is shut down immediately.
3.6
Current Limiting
PWM Latch
Latched Off
Mode
3.5.3
Gate Driver
FF1
Current Limiting
Spike
Blanking
190ns
1.66V
VCC
C11
PWM-Latch
Over Power Protection
OPP
1
Gate
Vcsth
Leading
C10
C12
Edge
Blanking
220ns
PWM-OP
&
G10
0.25V
Gate Driver
Figure 15
Gate Driver
1pF
10k
Active Burst
Mode
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the external power
MOSFET threshold. This is achieved by a slope control
of the rising edge at the gate driver’s output (see Figure
16).
D1
CS
Figure 17
Current Limiting Block
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the external power MOSFET is
sensed via an external sense resistor RSense. By means
of RSense the source current is transformed to a sense
voltage VSense which is fed into the pin CS. If the voltage
ca. t = 130ns
V
Sense exceeds the internal threshold voltage Vcsth, the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
5V
A Propagation Delay Compensation is added to
support the immediate shut down of the external power
MOSFET with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
output power can be reduced to minimal.
t
Figure 16
Gate Rising Slope
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Version 2.0
12
6 Dec 2007
INFINEON [ Infineon ]
