AIROC™ Bluetooth® system on chip for automotive applications
Peripherals
7.8
PDM microphone
The CYW89820 accepts a ΣΔ-based one-bit pulse density modulation (PDM) input stream and outputs filtered
samples at either 8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process
analog microphone signals and generate digital signals. The PDM inputs share the filter path with the aux ADC.
Two types of data rates can be supported:
• 8 kHz
• 16 kHz
The external digital microphone takes in a 2.4 MHz clock generated by the CYW89820 and outputs a PDM signal
which is registered by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable
through a programmable control bit. The design can accommodate two simultaneous PDM input channels, so
stereo voice is possible.
7.9
I2S interface
The CYW89820 supports a single I2S digital audio port with both master and slave modes. The I2S signals are:
• I2S clock: I2S SCK
• I2S word select: I2S WS
• I2S data out: I2S DO
• I2S data in: I2S DI
I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an
output. The channel word length is 16 bits and the data is justified so that the MSN of the left-channel data is
aligned with the MSB of the I2S bus, per I2S Specifications. The MSB of each data word is transmitted one bit clock
cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left Channel data is transmitted
when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYW89820
are synchronized with the falling edge of I2S SCK and should be sampled by the receiver on the rising edge of the
I2S SCK.
The clock rate in master mode as follows:
• 16 kHz 16 bits per frame = 256 kHz
The master clock is generated from the reference clock using an N/M clock divider. In the slave mode, any clock
rate is supported up to a maximum of 3.072 MHz.
7.10
PCM interface
The CYW89820 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode.
In master mode, the CYW89820 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are
provided by another master on the PCM interface and are inputs to the CYW89820.The configuration of the PCM
interface may be adjusted by the host through the use of vendor-specific HCI commands.
Note PCM interface shares HW with the I2S interface and only one can be used at any time. Only audio source
(other than SCO) use cases are supported on CYW89820.
7.10.1
Slot mapping
The CYW89820 supports up to three simultaneous full-duplex channels through the PCM Interface. These three
channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or
16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected
interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2,
4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same
slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM
interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last
bit of the slot.
Datasheet
19
002-25826 Rev. *G
2022-09-24
INFINEON [ Infineon ]
