BTS7040-1EPA
PROFET™ +2 12V
Diagnosis
9.4
SENSE Timings
Figure 40 shows the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load
change). As a proper signal cannot be established before the load current is stable (therefore before tON),
tsIS(DIAG) = tsIS(ON) + tON
.
IN
OFF
OFF
ON
t
t
DEN
tO FF
IL
t
t
tsIS(LC)
tsIS(O FF)
tsIS(ON)
tsIS(O FF)
tsIS(DI AG)
IIS
Diagnose_PROFET_SENSE_timings.emf
Figure 40 SENSE Settling / Disabling Timing
IN
OFF
OFF
ON
t
DEN
IL
t
t
tsIS(ON)_SLC
tsIS(ON)
tsIS(LC)_SLC
IIS
t
Diagnose_PROFET_SENSE_timings_SLC.emf
Figure 41 SENSE Timing with Small Load Current
Data Sheet
48
Rev. 1.10
2020-12-14
INFINEON [ Infineon ]
