AN985B/BX
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
System Diagram of the AN985B/BX 8
Block Diagram of the AN985B/BX 10
Pin Assignment (top view) 11
Ring Structure of Frame Buffer 18
Chain Structure of Frame Buffer 19
Transmit Pointers for Descriptor Management 20
Receive Pointers for Descriptor Management 21
Transmit Flow 22
Transmit Data Flow of Pre-fetch Data 23
Figure 10 Transmit Normal Interrupt and Early Interrupt Comparison 23
Figure 11 Receive Data Flow (without early interrupt and with early interrupt) 24
Figure 12 Detailed Receive Early Interrupt Flow 24
Figure 13 MAC Control Frame Format 29
Figure 14 PAUSE Operation Receive State Diagram 30
Figure 15 NIC, PHY, and I/O interconnection 91
Figure 16 Timing 92
Figure 17 PCI Clock Waveform 103
Figure 18 PCI Timings 104
Figure 19 Flash Write Timings 105
Figure 20 Flash Read Timings 106
Figure 21 Serial EEPROM Timing 107
Figure 22 Package Outline for the AN985B/BX 108
Data Sheet
6
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
