IN16C1054
Table 20: Auto Toggle Control Register Description
Bit
Symbol
Description
7
ATR[7]
RXEN Polarity Select.
0 : Asserted output of RXEN is ‘0’. (default)
1 : Asserted output of RXEN is ‘1’.
RXEN Control Mode Select.
6
ATR[6]
0 : RXEN is outputted as same as ATR[7], irrespective of TXD
signal. (default)
1 : RXEN is outputted after making complement of ATR[7] when
TXD signal is transmitting. And outputted as same as ATR[7]
when TXD is not transmitting.
5
4
ATR[5]
ATR[4]
TXEN Polarity Select.
0 : Asserted output of TXEN is ‘0’. (default)
1 : Asserted output of TXEN is ‘1’.
TXEN Control Mode Select.
Only when ATR[1:0] is ‘11’;
0 : TXEN is outputted as same as ATR[5], irrespective of TXD
signal. (default)
1 : RXEN is outputted after making complement of ATR[5] when
TXD signal is transmitting, and outputted after making
complement of ATR[7] when TXD is not transmitting..
Not used, always ‘00’.
3:2
1:0
ATR[3:2]
ATR[1:0]
Auto Toggle Enable.
00 : Auto toggle is disabled (default).
RTS#/TXEN, DTR#TXEN pin operate as RTS#, DTR#. If 80-
pin, each of TXRDY/TXEN, RXRDY/RXEN operates as
TXRDY, RXRDY.
01 : RTS#/TXEN pin operates as TXEN. DTR#/TXEN pin operates
as DTR#. If 80-pin, each of TXRDY/TXEN, RXRDY/RXEN
operates as TXRDY, RXRDY.
10 : DTR#/TXEN pin operates as TXEN. RTS#/TXEN operates as
RTS#. If 80-pin, each of TXRDY/TXEN, RXRDY/RXEN
operates as TXRDY, RXRDY.
11 : Only in 80-pin. TXRDY/TXEN, RXRDY/RXEN pin operates as
TXEN, RXEN. RTS#/TXEN, DTR#/TXEN operates as RTS#,
DTR#.
7.19 Enhanced Feature Register (EFR, Page 3)
EFR enables or disables the enhanced features of the UART. Table 21 shows EFR bit
settings.
Table 21: Enhanced Feature Register Description
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
