IN16C1054
Bit
Symbol
Description
7:6
5
AFR[7:6]
AFR[5]
Not used, always ‘00’.
Global Interrupt Polarity Select
0 : GINT pin outputs ‘0’ when interrupt is generated (default).
1 : GINT pin outputs ‘1’ when interrupt is generated.
4
AFR[4]
Global Interrupt Enable
0 : INT0/GINT pin is selected to INT0 (default).
1 : INT0/GINT pin is selected to GINT.
3:1
0
AFR[3:1]
AFR[0]
Not used, always ‘000’.
256-byte FIFO Enable.
0 : 256-byte FIFO mode is disabled and this means SB16C1054
operates as Non FIFO mode or 64-byte FIFO mode (default).
1 : 256-byte FIFO mode is enabled and ISR[7:6] operates as
256-TX FIFO Empty and 256-RX FIFO Full.
7.24 Xoff Re-transmit Count Register (XRCR, Page 4)
XRCR operates only when Software flow control is enabled by EFR[3:0] and Xoff Re-
transmit function of MCR[2] is also enabled. And it determines the period of
retransmission of Xoff character. Table 23 shows XRCR bit settings.
Table 23: Xoff Re-transmit Count Register Description
Bit
Symbol
Description
7:2
1:0
XRCR[7:2] Not used, always ‘0000_00’.
XRCR[1:0] Xoff Re-transmit Count Select
00 : Transmits Xoff character whenever the number of received
data is 1 during XOFF status. (default)
01 : Transmits Xoff character whenever the number of received
data is 4 during XOFF status.
10 : Transmits Xoff character whenever the number of received
data is 8 during XOFF status.
11 : Transmits Xoff character whenever the number of received
data is 16 during XOFF status.
7.25 Transmit FIFO Trigger Level Register (TTR, Page 4)
Operates only when 256-byte FIFO mode is enabled. It sets the trigger level of 256-byte
TX FIFO for generating transmit interrupt. Interrupt is generated when the number of data
remained in TX FIFO after transmitting through TXD pin is less than the value of TTR.
Initial value is 128h, ‘1000_0000’ and ‘0000_0000’ must not be written. If written,
unexpected operation may occur.
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
