IN16C1054
7.12 Global Interrupt Control Register (GICR, Page 2)
GICR is a register that internal four 16C1050 UARTs share to use. It is used when
determining whether each interrupt generated at four 16C1050 UARTs are transmitted to
global interrupts or not. Table 16 shows the GICR bit settings.
Table 16: Global Interrupt Control Register Description
Bit
7:1
0
Symbol
GICR[7:1]
GICR[0]
Description
Not used, always ‘000_0000’
Global Interrupt Mask.
0 : Deasserted, irrespective of occurring interrupts of four
16C1050 UARTs displayed on GISR[3:0]. ‘1’ is
outputted if global interrupt polarity, AFR[5] is ‘0’ and
outputted ‘0’ if ‘1’.
1 : Generates interrupt when all the values of GISR[3:0]
are not ‘0’. If all the values of GISR[3:0] are ‘0’, interrupt
is not outputted on GINT pin. ‘1’ is outputted if AFR[5] is
‘0’ and ‘0’ is outputted if ‘1’.
7.13 Global Interrupt Status Register (GISR, Page 2)
GISR is a register that internal four 16C1050 UARTs share to use. It is used to verify the
generation status of each interrupt of four 16C1050 UARTs when global interrupt function
is enabled. Table 17 shows GISR bit settings.
Table 17: Global Interrupt Status Register Description
Bit
7
Symbol
GISR[7]
GISR[6:4]
GISR[3]
Description
Mirror the content of GICR[0].
6:4
3
Not used, always ‘00’.
UART of CS3# Interrupt Status.
0 : UART of CS3# interrupt was not generated.
1 : UART of CS3# interrupt was generated.
UART of CS2# Interrupt Status.
2
1
0
GISR[2]
GISR[1]
GISR[0]
0 : UART of CS2# interrupt was not generated.
1 : UART of CS2# interrupt was generated.
UART of CS1# Interrupt Status.
0 : UART of CS1# interrupt was not generated.
1 : UART of CS1# interrupt was generated.
UART of CS0# Interrupt Status.
0 : UART of CS0# interrupt was not generated.
1 : UART of CS0# interrupt was generated.
7.14 Transmit FIFO Count Register (TCR, Page 2)
Rev. 00
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